1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device which reduces a leakage current and improves its operating speed while electrically connecting an element of a memory cell region with that of a peripheral circuit region in an excellent state and a method of fabricating the same.
2. Description of the Prior Art
First, a method of fabricating a first exemplary conventional dynamic random access memory (hereinafter referred to as a DRAM), i.e., an exemplary conventional semiconductor device, is now described with reference to FIGS. 54 to 78.
Referring to FIG. 54, element isolation oxide films 2a and 2b are formed on prescribed regions of a silicon substrate 1 by trench isolation, for forming a memory cell region 1a and a peripheral circuit region 1b. 
Referring to FIG. 55, boron is injected into the memory cell region la and a first area of the peripheral circuit region 1b, for forming p-type wells 3a and 3b respectively.
Referring to FIG. 56, phosphorus is injected into a second area of the peripheral circuit region 1b, for forming an n-type well 4.
Referring to FIG. 57, a gate oxide film 5 is formed on the silicon substrate 1 by thermal oxidation or the like. A polysilicon film and a tungsten silicide film 6 are formed on the gate oxide film 5. A silicon oxide film 7 is formed on the tungsten silicide film 6. Thereafter gate electrode portions 8a, 8b and 8c are formed by photolithography and etching.
Referring to FIG. 58, the n-type well 4 is covered with a photoresist pattern 48a and thereafter phosphorus is injected by ion implantation, for forming nxe2x88x92 source/drain regions 9a, 9b, 9c and 9d. Thereafter the photoresist pattern 48a is removed.
Referring to FIG. 59, the p-type wells 3a and 3b are covered with a photoresist pattern 48b and thereafter boron is injected by ion implantation, for forming pxe2x88x92 source/drain regions 10a and 10b. Thereafter the photoresist pattern 48b is removed.
Referring to FIG. 60, a silicon oxide film 11 is formed on the silicon substrate 1, to cover the gate electrode portions 8a, 8b and 8c. 
Referring to FIG. 61, the silicon oxide film 11 is anisotropically etched for forming sidewall oxide films 12 on both side surfaces of the gate electrode portions 8a, 8b and 8c respectively.
Referring to FIG. 62, a photoresist film 48c is formed to cover the n-type well 4. Thereafter the photoresist film 48c is employed as a mask for injecting phosphorus by ion implantation, thereby forming n+ source/drain regions 13a, 13b, 13c and 13d. Thus formed is a MOS transistor T1 of an LDD structure including n-type source/drain regions 15a and 15b and the gate electrode portion 8a. Further formed is a MOS transistor T2 of an LDD structure including n-type source/drain regions 15c and 15d and the gate electrode portion 8b. Thereafter the photoresist film 48c is removed.
Referring to FIG. 63, a photoresist film 48d is formed to cover the p-type wells 3a and 3b. Thereafter the photoresist film 48d is employed as a mask for injecting boron by ion implantation, thereby forming p+ source/drain regions 14a and 14b. Thus formed is a MOS transistor T3 including p-type source/drain regions 16a and 16b and the gate electrode portion 8c. Thereafter the photoresist film 48d is removed.
Referring to FIG. 64, a silicon oxide film 17 is formed on the silicon substrate 1 to cover the gate electrode portions 8a, 8b and 8c. 
Referring to FIG. 65, a bit line contact hole 18 exposing a surface of the n-type source/drain region 15b is formed in the silicon oxide film 17.
Referring to FIG. 66, a polysilicon film 40 is buried in the bit line contact hole 18.
Referring to FIG. 67, a bit line 25 electrically connected to the polysilicon film 40 is formed on the silicon oxide film 17.
Referring to FIG. 68, a silicon oxide film 26 is formed on the silicon oxide film 17, to cover the bit line 25.
Referring to FIG. 69, a storage node contact hole 41a exposing a surface of the n-type source/drain region 15a is formed in the silicon oxide films 17 and 26.
Referring to FIG. 70, a polysilicon film 42 is buried in the storage node contact hole 41a. 
Referring to FIG. 71, a metal film of ruthenium or platinum is formed on the silicon oxide film 26, and a storage node 28a is formed by prescribed photolithography and etching.
Referring to FIG. 72, a thin film of a high dielectric constant and a metal film of ruthenium or platinum are successively formed on the storage node 28a. Thereafter a capacitor dielectric film 28b and a cell plate 28c are formed by prescribed photolithography and etching. The storage node 28a, the capacitor dielectric film 28b and the cell plate 28c form a capacitor 28.
Referring to FIG. 73, an interlayer insulation film 29 is formed on the silicon oxide film 26, to cover the capacitor 28.
Referring to FIG. 74, peripheral circuit contact holes 43a and 43b exposing surfaces of the n-type source/drain regions 15d and 15c are formed in the interlayer insulation film 29 and the silicon oxide films 17 and 26. Further, peripheral contact holes 43c and 43d are formed to expose surfaces of the p-type source/drain regions 16a and 16b. At the same time, a cell plate contact hole 30 is formed to expose a surface of the cell plate 28c of the capacitor 28.
Referring to FIG. 75, a titanium film 45 and a titanium nitride film 47a are formed in the cell plate contact hole 30 by sputtering or the like. Further, titanium films 22c, 22d, 22e and 22f and titanium nitride films 47b, 47c, 47d and 47e are formed in the peripheral circuit contact holes 43a, 43b, 43c and 43d respectively. FIG. 76 shows a portion around the n-type source/drain region 15d and the p-type source/drain region 16b in this step in an enlarged manner.
Thereafter heat treatment is performed to react the titanium films 22c, 22d, 22e and 22f with silicon contained in the n-type source/drain regions 15a, 15b, 15c and 15d and the p-type source/drain regions 16a and 16b, for forming titanium silicide films 24c, 24d, 24e and 24f. FIG. 77 shows the portion around the n-type source/drain region 15d and the p-type source/drain region 16b in this step.
Referring to FIG. 78, an aluminum copper film is formed on the interlayer insulation film 29, and metal wires 33 are formed by prescribed photolithography and etching. Thereafter an interlayer insulation film (not shown) and a passivation film (not shown) are formed to cover the metal wires 33, thereby completing the DRAM.
A method of fabricating a second exemplary conventional DRAM is now described with reference to FIGS. 79 to 86. After a step similar to that shown in FIG. 63 described with reference to the first prior art, a silicon nitride film 56 is formed on a semiconductor substrate 1 to cover gate electrode portions 8a, 8b and 8c, as shown in FIG. 79.
Referring to FIG. 80, a part of the silicon nitride film 56 formed on a peripheral circuit region 1b is removed. A silicon oxide film 17 is formed to cover the silicon nitride film 56 and the gate electrode portions 8b and 8c. A photoresist film 48g is formed on the silicon oxide film 17. This photoresist film 48g is employed as a mask for anisotropically etching the silicon oxide film 17, thereby forming an opening 62 exposing a surface of the silicon nitride film 56.
Referring to FIG. 81, the photoresist film 48g is employed as a mask to anisotropically etch the silicon nitride film 56, for forming a bit line contact hole 18c exposing a surface of an n-type source/drain region 15b. Thereafter the photoresist film 48g is removed. Referring to FIG. 82, a polysilicon film 40 is formed to fill up the bit line contact hole 18c. A bit line 25 electrically connected to the polysilicon film 40 is formed on the silicon oxide film 17.
Referring to FIG. 83, a silicon nitride film (not shown) is formed on the silicon oxide film 17. Prescribed etching is performed on the silicon nitride film, to leave a silicon nitride film 57a only on surfaces of the bit line 25. Referring to FIG. 84, a silicon oxide film 26 is formed on the silicon oxide film 17, to cover the silicon nitride film 57a. A photoresist film 48h is formed on the silicon oxide film 26. The photoresist film 48h is employed as a mask to anisotropically etch the silicon oxide films 26 and 16, for forming an opening 63 exposing a surface of the silicon nitride film 56.
Referring to FIG. 85, the silicon nitride film 56 is further anisotropically etched through the photoresist film 48h serving as a mask, thereby forming a storage node contact hole 41a exposing a surface of an n-type source/drain region 15a. Thereafter steps similar to those of the first prior art shown in FIGS. 70 to 78 are carried out, thereby obtaining the DRAM having a structure shown in FIG. 86.
In the memory cell region 1a of the DRAM according to the first or second prior art formed in the aforementioned manner, the storage node 28a of the capacitor 28 is electrically connected with the n-type source/drain region 15a of the MOS transistor T1 through the polysilicon film 42 buried in the storage node contact hole 41a. Further, the bit line 25 is electrically connected with the n-type source/drain region 15b of the MOS transistor T1 through the polysilicon film 40 buried in the bit line contact hole 18.
In the peripheral circuit region 1b, on the other hand, the wiring layers 33 are electrically connected with the n-type source/drain regions 15c and 15d of the MOS transistor T2 through the titanium silicide films 24c and 24d and the titanium nitride films 47b and 47c buried in the peripheral circuit contact holes 43a and 43b respectively. Further, the wiring layers 33 are electrically connected with the p-type source/drain regions 16a and 16b of the MOS transistor T3 through the titanium silicide films 24e and 24f and the titanium nitride films 47d and 47e buried in the peripheral circuit contact holes 43c and 43d respectively.
The reason for this is as follows: If a titanium nitride film and a titanium silicide film are formed in the storage node contact hole 41a of the memory cell region 1a, silicon contained in the source/drain region 15a is consumed in formation of the titanium silicide film, to result in an increased leakage current from the source/drain region 15a to the silicon substrate 1. If polysilicon films are formed in the peripheral circuit contact holes 43a, 43b, 43c and 43d of the peripheral circuit region 1b, on the other hand, the electrical resistance is so increased that no high-speed operation can be attained.
Thus, the polysilicon film 42 is formed in the storage node contact hole 41a in the memory cell region 1a, in order to reduce the leakage current. In the peripheral circuit region 1b, on the other hand, the titanium films 22c, 22d, 22e and 22f and the titanium nitride films 47b, 47c, 47d and 47e are formed in the peripheral circuit contact holes 43a, 43b, 43c and 43d respectively, in order to attain a high-speed operation rather than reduction leakage currents.
However, the DRAM according to each of the first prior art and the second prior art has the following problems: Due to increased storage capacity of the DRAM, refinement so progresses that it is estimated that the hole diameter of the bit line contact hole 18 or the storage node contact hole 41a of the memory cell region 1a is about 0.08 xcexcm in a 1-Gbit DRAM, for example. It is also estimated that the depths of the bit line contact hole 18 and the storage node contact hole 41a are about 0.5 xcexcm and about 0.8 xcexcm respectively.
When the polysilicon films 40 and 42 are formed in the bit line contact hole 18 and the storage node contact hole 41a respectively, the electrical resistance thereof is increased in inverse proportion to the sectional areas of the contact holes 18 and 41a. It is conceivable that the operating speed of a memory cell in the memory cell region la cannot be increased as a result and it is difficult to attain a higher operating speed of the DRAM.
If titanium silicide films and titanium nitride films are formed in the storage node contact hole 41a and the bit line contact hole 18 of the memory cell region 1a in order to solve this problem, silicon contained in the n-type source/drain regions 15a and 15b is consumed in formation of the titanium silicide films, as described above. It is supposed that leakage currents flowing from the n-type source/drain regions 15a and 15b to the silicon substrate 1 are consequently increased.
On the other hand, it is estimated that the hole diameter and the depth of the peripheral circuit contact holes 43a, 43b, 43c and 43d in the peripheral circuit region 1b are about 0.15 xcexcm and about 1.0 xcexcm respectively. Thus, it is estimated that the aspect ratio of the hole diameter to the depth of the peripheral circuit contact holes 43a, 43b, 43c and 43d exceeds 6. Consequently, it is conceivably difficult to form the peripheral circuit contact holes 43a, 43b, 43c and 43d having a high aspect ratio in the interlayer insulation film 29 and the silicon oxide films 17 and 26.
When the cell plate contact hole 30 and the peripheral circuit contact holes 43a, 43b, 43c and 43d are simultaneously formed in the memory cell region la and the peripheral circuit region 1b respectively, further, the cell plate 28c is damaged by etching after its surface is exposed and before the surfaces of the n-type source/drain regions 15c and 15d and the p-type source/drain regions 16a and 16b are exposed. Thus, the cell plate contact hole 30 may be formed to pass through the cell plate 28c. In this case, it is conceivable that the capacitor 28 is electrically connected with the MOS transistors T2 and T3 of the peripheral circuit region 1b in an inferior state.
In the DRAM according to the second prior art, further, the following two problems are supposed in addition to the aforementioned problems: FIG. 87 illustrates the plane structure under the silicon nitride film 56 in the steps of forming the bit line contact hole 18c shown in FIGS. 80 and 81. FIGS. 80 and 81 show a section taken along the line L3xe2x80x94L3 in FIG. 87 in particular. Referring to FIG. 87, the opening 62 is formed to be located on a substantially central position of the n-type source/drain region 15b, in particular.
If the photoresist film 48g is misaligned in photolithography, however, some opening 62a may be formed over a part of the gate electrode 8a. In this case, etching must be further continued after a portion of the silicon nitride film 56 located on a shoulder portion of the gate electrode 8a is exposed to remove the silicon oxide film 17a in order to form the opening 62a, as shown in FIG. 88. FIG. 88 is a sectional view taken along the line L4xe2x80x94L4 in FIG. 87.
Particularly in a 1-Gbit DRAM, it is necessary to form a fine bit line contact hole having a large aspect ratio, as hereinabove described. In formation of the opening 62a in the actual process, therefore, gas ions for etching must indispensably be introduced into a deep portion of the opening 62a as shown by arrows, by setting an alternating voltage applied to the semiconductor substrate 1 at a relatively high level in an etching device.
In this case, however, it is supposed that the already exposed portion of the silicon nitride film 56 is eroded by the etching while the silicon oxide film 17a is removed, to expose the sidewall oxide film 12 as well as the polysilicon film 6 of the gate electrode portion 8a. If the bit line 25 is connected to the n-type source/drain region 15b of the MOS transistor T1 through the polysilicon film 40 buried in the bit line contact hole 18 in this case, the electrical connection is so inferiorly performed that the bit line 25 and the gate electrode 8a may be shorted depending on the degree of the etching. It is supposed that the MOS transistor T1 abnormally operates as a result.
A further problem is now described. FIG. 89 illustrates the plane structure under the bit line 25 in the step shown in FIG. 84. The section shown in FIG. 84 is taken along the line L5xe2x80x94L5 in FIG. 89. Referring to FIG. 89, the opening 63 is formed to be located on a substantially central position of the n-type source/drain region 15a in particular.
If the photoresist film 48h is misaligned in photolithography, however, some opening 63a may be formed over a part of the bit line 25. In this case, etching must be further continued after a portion of the silicon nitride film 57a formed on the surfaces of the bit line 25 is exposed to remove the silicon oxide films 26 and 17, as shown in FIG. 90. Therefore, it is supposed that the already exposed portion of the silicon nitride film 57a is eroded by excessive etching before the silicon oxide film 17 is removed in formation of the opening 63a, to expose the surfaces of the bit line 25. It is also supposed that the storage node 28a is electrically shorted with the bit line 25 through the polysilicon film 42 buried in the storage node contact hole 41a. It is further supposed that no desired operating characteristics of the DRAM are attained as a result. FIG. 90 shows a section taken along the line L6xe2x80x94L6 in FIG. 89.
The present invention has been proposed in order to solve the aforementioned supposable problems, and an object thereof is to provide a semiconductor device which reduces a leakage current, suppresses an electrical short and attains a high-speed operation while readily forming each contact hole and electrically connecting elements of a memory cell region and a peripheral circuit region with each other in an excellent state. Another object of the present invention is to provide a method of fabricating such a semiconductor device.
The semiconductor device according to the present invention comprises a semiconductor substrate, a first region, a first impurity region, a first conductor layer, a second conductor layer, a third conductor layer, a first insulator layer and a first conductor region. The semiconductor substrate has a major surface. The first region is formed on the major surface of the semiconductor substrate. The first impurity region is formed on a surface of the first region. The first conductor layer is formed on a surface of the first impurity region. The second conductor layer is formed on the first conductor layer. The third conductor layer is formed on the second conductor layer. The first insulator layer is formed on the semiconductor substrate to enclose the first to third conductor layers. The first conductor region is formed on the first insulator layer, and electrically connected with the third conductor layer. The first conductor layer contains silicon. The second conductor layer contains a compound of silicon and a prescribed metal. The third conductor layer contains the prescribed metal or a compound of this metal.
According to this structure, the first conductor region and the first impurity region are electrically connected with each other through the first to third conductor layers. Particularly when the second conductor layer is formed by heat treatment, the metal consumes the silicon contained in the first conductor layer. Thus, the first impurity region can be prevented from being influenced by the heat treatment. Consequently, a leakage current flowing from the first conductor region to the semiconductor substrate through the first impurity region is reduced. The second and third conductor layers contain the metal or the compound of the metal, whereby the electrical resistance between the first conductor region and the first impurity region can be reduced. Consequently, the operating speed of the semiconductor device is improved.
According to a first preferred aspect of the inventive semiconductor device, the first insulator layer has a first contact hole exposing a surface of the first conductor layer, and the second and third conductor layers are formed in the first contact hole.
In this case, etching ends on an upper surface of the first conductor layer in formation of the first contact hole, to be inhibited from damaging the region under the first conductor layer.
According to a second preferred aspect of the present invention, the semiconductor device further includes a pair of source/drain regions which are provided on the major surface of the first region at a space and a gate electrode which is formed on a region of the semiconductor substrate held between the source/drain regions with a gate insulator film interposed, the first one of the pair of source/drain regions includes the first impurity region, and the first conductor layer is formed in the vicinity of the gate electrode to partially cover the gate electrode while being electrically insulated from the gate electrode.
In this case, etching ends on the upper surface of the first conductor layer in formation of the first contact hole, to be inhibited from influencing the gate electrode. Consequently, the electrical insulation between the first conductor region and the gate electrode is improved, and the semiconductor device attains excellent electrical connection between the first conductor region and the source/drain regions.
According to a third preferred aspect of the present invention, the semiconductor device further includes a second impurity region which is formed on a major surface of the first region at a space from the first impurity region, a fourth conductor layer containing silicon which is formed on a surface of the second impurity region, a first protective layer which is formed to cover a surface of the first conductor region, and a second insulator layer which is formed on the first insulator layer to cover the first protective layer. The first and second insulator layers have a second contact hole exposing a surface of the fourth conductor layer. The semiconductor device further includes a fifth conductor layer, containing a compound of silicon and the prescribed metal, which is formed in the second contact hole and electrically connected with the fourth conductor layer, a sixth conductor layer, containing the prescribed metal or a compound of this metal, which is formed on the fifth conductor layer in the second contact hole, and a second conductor region which is formed on the second insulator layer and electrically connected with the sixth conductor layer.
In this case, the depth of the second contact hole is reduced by a value corresponding to the thickness of the fourth conductor layer to reduce the aspect ratio of the second contact hole as compared with the case of forming a contact hole directly exposing the surface of the second impurity region in formation of the second contact hole in the first and second insulator layers for electrically connecting the second conductor region and the second impurity region with each other. Even if the first conductor region is exposed due to misalignment or the like in formation of the second contact hole, therefore, the surface of the first conductor region can be inhibited from exposure resulting from excessive etching of the first protective layer. Consequently, the first and second conductor regions can be prevented from an electrical short by the fifth and sixth conductor layers formed in the second contact hole.
According to a fourth preferred aspect of the inventive semiconductor device, the second one of the pair of source/drain regions includes the second impurity region, and the gate electrode is formed on a region held between the first and second impurity regions.
In this case, a MOS transistor is so formed that the first and second conductor regions are connected to the first and second ones of the pair of source/drain regions respectively. This MOS transistor is electrically connected with the first and second conductor regions in an excellent state. Consequently, a semiconductor device including a MOS transistor which is prevented from an electrical short is obtained.
According to a fifth preferred aspect of the inventive semiconductor device, the first protective layer is a silicon nitride film, and the second insulator layer is a silicon oxide film.
In this case, the silicon oxide film can be readily selectively etched while substantially leaving the silicon nitride film in formation of the second contact hole. Thus, the surface of the first conductor region can be effectively inhibited from exposure.
According to a sixth preferred aspect of the present invention, the semiconductor device further includes a second region which is formed on the major surface of the semiconductor substrate and electrically insulated from the first region, a third impurity region which is formed on a surface of the second region, and a third insulator layer which is formed on the second insulator layer to cover the first and second regions. The first and second insulator layers have a third contact hole exposing a surface of the third impurity region. The third insulator layer has a fourth contact hole communicating with the third contact hole. The third insulator layer has a fifth contact hole exposing a surface of the second conductor region. The semiconductor device further includes a first columnar conductor which is formed in the third contact hole and electrically connected with the third impurity region, a second columnar conductor which is formed in the fourth contact hole and electrically connected with the first columnar conductor, a third columnar conductor which is formed in the fifth contact hole, a first wiring layer which is electrically connected with the second columnar conductor and formed on the third insulator layer, and a second wiring layer which is electrically connected with the third columnar conductor and formed on the third insulator layer.
In this case, the third columnar conductor electrically connects the first wiring layer on the first region with the second conductor region. The first and second columnar conductors electrically connect the second wiring layer on the second region with the third impurity region. The first columnar conductor is formed in the third contact hole. The second columnar conductor is formed in the fourth contact hole. The third columnar conductor is formed in the fifth contact hole. The third contact hole has a depth corresponding to the thickness of the first and second insulator layers, and the fourth contact hole has a depth corresponding to the thickness of the third insulator layer. As compared with the case of forming contact holes having depths corresponding to the thicknesses of the first to third insulator layers, therefore, the depths of the third and fourth contact holes are further reduced to reduce the aspect ratios respectively. Thus, the third and fourth contact holes are further readily formed and inhibited from defective opening, whereby the electrical connection between the second wiring layer and the third impurity region is improved. In simultaneous formation of the fourth and fifth contact holes, the exposed part of the surface of the second conductor region is exposed to etching gas for a time corresponding to that up to exposure of a surface of the first columnar conductor on the bottom of the fourth contact hole. As compared with the case of forming a contact hole directly exposing the surface of the third impurity region, therefore, the time for exposing the exposed part to the etching gas is reduced. Thus, the fifth contact hole can be prevented from partially passing through the second conductor region due to excessive etching of the second conductor region. Consequently, the first wiring layer is electrically connected with the second conductor region in an excellent state.
According to a seventh preferred aspect of the inventive semiconductor device, the first and second wiring layers are formed by the same layer.
In this case, the electrical connection between the second conductor region of the first region and the third impurity region of the second region is improved.
According to an eighth preferred aspect of the present invention, the semiconductor device further includes a relay conductor, larger in sectional area than the first columnar conductor, which is formed on the second insulator layer to intervene between the first and second columnar conductors.
In this case, the depth of the fourth contact hole is reduced by a value corresponding to the thickness of the relay conductor. Thus, the aspect ratio of the fourth contact hole is further reduced, so that the fourth contact hole can be readily formed. Further, the relay conductor has a larger sectional area than the first columnar conductor, whereby a surface of the relay conductor can be reliably exposed even if misalignment is caused in photolithography in formation of the fourth contact hole. Thus, the electrical connection between the second wiring layer and the third impurity region is further improved.
According to a ninth preferred aspect of the inventive semiconductor device, the relay conductor is formed by the same layer as the second conductor layer.
In this case, the relay conductor can be simultaneously formed in formation of the second conductor region, with no requirement for an additional step for forming the relay conductor.
According to a tenth preferred aspect of the inventive semiconductor device, the first region includes a plurality of element forming regions and an element isolation region for electrically insulating the element forming regions from each other, the gate electrode includes a first gate electrode portion extending on each element forming region and a second gate electrode portion, which is connected with the first gate electrode, extending on the element isolation region, and the semiconductor device further includes a second protective layer which is formed under the first insulator layer to cover the second gate electrode portion.
In this case, an opening having a relatively large opening area can be formed in the first insulator layer located in each element forming region. In other words, an opening having a reduced aspect ratio can be formed. Thus, a part of the second protective layer, which is formed to cover the gate electrode at first, covering the first gate electrode portion in the element forming region in particular is excessively etched so that only the second protective layer is exposed on the bottom of the opening without exposing the first gate electrode portion. When the exposed part of the second protective layer is thereafter removed, the surfaces of the first and second impurity regions are exposed substantially with no etching of the first gate electrode portion extending on each element forming region. The remaining part of the second protective layer covering the second gate electrode portion extending on the element isolation region is left unremoved. Thus, an opening for forming each element forming region can be readily formed in the first insulator layer without substantially etching the first gate electrode portion.
According to an eleventh preferred aspect of the inventive semiconductor device, the second protective layer is a silicon nitride film, and the first insulator layer is a silicon oxide film.
In this case, the silicon oxide film can be readily selectively etched while substantially leaving the silicon nitride film.
According to a twelfth preferred aspect of the present invention, the semiconductor device further includes a third region which is formed on the major surface of the semiconductor substrate and electrically insulated from the first region, a fourth impurity region which is formed on a surface of the third region, and a fourth insulator layer which is formed on the first insulator layer to cover the first and third regions. The first insulator layer has a sixth contact hole exposing a surface of the fourth impurity region. The fourth insulator layer has a seventh contact hole communicating with the sixth contact hole. The fourth insulator layer also has an eighth contact hole exposing the surface of the first conductor region. The semiconductor device further includes a fourth columnar conductor which is formed in the sixth contact hole and electrically connected with the fourth impurity region, a fifth columnar conductor which is formed in the seventh contact hole and electrically connected with the fourth columnar conductor, a sixth columnar conductor which is formed in the eighth contact hole, and a third wiring layer which is electrically connected with the fifth and sixth columnar conductors and formed on the fourth insulator layer.
In this case, the sixth columnar conductor electrically connects the third wiring layer on the first region with the first conductor region. The fourth and fifth columnar conductors electrically connect the third wiring layer on the third region with the fourth impurity region. The fourth columnar conductor is formed in the sixth contact hole. The fifth columnar conductor is formed in the seventh contact hole. The sixth columnar conductor is formed in the eighth contact hole. The sixth and seventh contact holes have depths corresponding to the thicknesses of the first and fourth insulator layers respectively. As compared with the case of forming a contact hole having a depth corresponding to the total thickness of the first and fourth insulator layers, therefore, the depths of the sixth and seventh contact holes are further reduced and the aspect ratios thereof are also reduced respectively. Thus, the sixth and seventh contact holes can be further readily formed and inhibited from defective opening, whereby the electrical connection between the third wiring layer and the fourth impurity region is improved. In simultaneous formation of the seventh and eighth contact holes, the exposed part of the surface of the first conductor region is exposed to etching gas for a time corresponding to that up to exposure of the surface of the fourth columnar conductor on the bottom of the seventh contact hole. As compared with the case of forming a contact hole directly exposing the surface of the fourth impurity region, therefore, the time for exposing the exposed part to the etching gas is reduced. Thus, the eighth contact hole can be prevented from partially passing through the first conductor region due to excessive etching of the first conductor region. Consequently, the first conductor region is electrically connected with the fourth impurity region in an excellent state through the third wiring layer.
According to a thirteenth preferred aspect of the inventive semiconductor device, the semiconductor substrate is a single-crystalline silicon substrate, and the first conductor layer contains silicon or a silicon-germanium alloy.
In this case, the first conductor layer can be readily formed on a prescribed region of the semiconductor substrate in self alignment.
According to a fourteenth preferred aspect of the inventive semiconductor device, the prescribed metal includes any metal selected from a group consisting of titanium, cobalt, zirconium and hafnium.
In this case, the silicon contained in the first conductor layer and the metal readily cause silicide reaction in formation of the second conductor layer. Thus, metal silicide is readily formed.
The method of fabricating a semiconductor device according to the present invention comprises the following steps: A first impurity region is formed on a major surface of a semiconductor substrate. A first conductor layer containing silicon is formed on a surface of the first impurity region. A conductive material layer containing a prescribed metal is formed on the first conductor layer and heat-treated, thereby forming a second conductor layer containing a compound of the silicon contained in the first conductor layer and the prescribed metal. A third conductor layer containing a metal or a compound of this metal is formed on the second conductor layer. A first insulator layer is formed on the semiconductor substrate to enclose the first to third conductor layers. A first conductor region electrically connected to the third conductor layer is formed on the first insulator layer.
According to this method, the metal reacts with the silicon contained in the first conductor layer to form metal silicide in formation of the second conductor layer by the heat treatment. Thus, the first impurity region is inhibited from being influenced by the heat treatment. Consequently, a leakage current flowing from the first conductor region to the semiconductor substrate through the first impurity region is suppressed. Further, the second conductor layer containing the metal or the compound of the metal and the third conductor layer reduce the electrical resistance between the first conductor region and the first impurity region. Consequently, a semiconductor device suppressing a leakage current and attaining improvement of its operating speed etc. can be readily fabricated.
According to a first preferred aspect of the inventive method of fabricating a semiconductor device, the steps of forming the second and third conductor layers include steps of forming a first contact hole exposing a surface of the first conductor layer in the first insulator layer and forming the second and third conductor layers in the first contact hole.
In this case, etching ends on an upper surface of the first conductor layer in formation of the first contact hole, to be inhibited from damaging the region under the first conductor layer. As compared with the case of forming a contact hole exposing a surface of the first impurity region, the depth of the first contact hole can be reduced by a value corresponding to the thickness of the first conductor layer and the aspect ratio thereof is also reduced. Consequently, the first contact hole can be readily formed.
According to a second preferred aspect of the present invention, the method of fabricating a semiconductor device further includes steps of forming a gate electrode on the major surface of the semiconductor substrate with a gate insulator film interposed and forming a pair of source/drain regions on the major surface of the semiconductor substrate both sides of the gate electrode, the step of forming the source/drain regions includes the step of forming the first impurity region, and the step of forming the first conductor layer includes a step of forming the same in the vicinity of the gate electrode to partially cover the gate electrode while being electrically insulated from the gate electrode.
In this case, etching ends on the upper surface of the first conductor layer in formation of the first contact hole, to be inhibited from influencing the gate electrode. Thus, the electrical connection between the first conductor region and the source/drain regions can be improved.
According to a third preferred aspect of the present invention, the method of fabricating a semiconductor device further includes steps of forming a second impurity region on the major surface of the semiconductor substrate at a space from the first impurity region and forming a fourth conductor layer containing silicon on the second impurity region in advance of the step of forming the first insulator layer. The method further includes steps of forming a first protective layer on the surface of the first conductor region, forming a second insulator layer on the first insulator layer to cover the first protective layer, forming a second contact hole exposing a surface of the fourth conductor layer in the first and second insulator layers, forming a conductive material layer containing a prescribed metal in the second contact hole and simultaneously heat-treating the same thereby forming a fifth conductor layer containing a compound of the silicon contained in the fourth conductor layer and the aforementioned prescribed metal, forming a sixth conductor layer containing a metal or a compound of this metal on the fifth conductor layer in the second contact hole, and forming a second conductor region electrically connected with the sixth conductor layer on the second insulator layer.
In this case, the depth of the second contact hole is reduced by a value corresponding to the thickness of the fourth conductor layer and the aspect ratio thereof is also reduced in formation of the second contact hole in the first and second insulator layers as compared with the case of forming a contact hole directly exposing the surface of the second impurity region. Thus, the second contact hole can be formed in a shorter time. Even if the first conductor region is exposed due to misalignment or the like in formation of the second contact hole, therefore, the surface of the first conductor region can be inhibited from exposure resulting from excessive etching of the first protective layer. Consequently, the first and second conductor regions can be prevented from an electrical short by the fifth and sixth conductor layers formed in the second contact hole.
According to a fourth preferred aspect of the inventive method of fabricating a semiconductor device, the step of forming the pair of source/drain regions includes the steps of forming the first and second impurity regions, and the step of forming the gate electrode includes a step of forming the same on a region of the semiconductor substrate held between the first and second impurity regions.
In this case, a MOS transistor is so formed that the first and second conductor regions are connected to the first and second ones of the pair of source/drain regions respectively. Further, the first and second conductor regions can be prevented from an electrical short.
According to a fifth preferred aspect of the inventive method of fabricating a semiconductor device, a silicon nitride film is employed as the first protective layer, and a silicon oxide film is employed as the second insulator layer.
In this case, the silicon oxide film can be readily selectively etched while substantially leaving the silicon nitride film in formation of the second contact hole. Thus, the surface of the first conductor region can be effectively inhibited from exposure.
According to a sixth preferred aspect of the present invention, the method of fabricating a semiconductor device further includes steps of forming a first region including the first and second impurity regions, forming a second region which is electrically insulated from the first region on the major surface of the semiconductor substrate, and forming a third impurity region on a major surface of the second region in advance of the step of forming the first insulator layer. The method further includes steps of forming a third contact hole exposing a surface of the third impurity region in the first and second insulator layers, forming a first columnar conductor in the third contact hole, forming a third insulator layer on the second insulator layer to cover surfaces of the second conductor region and the first columnar conductor, forming fourth and fifth contact holes exposing surfaces of the first columnar conductor and the second conductor region respectively in the third insulator layer, forming a second columnar conductor in the fourth contact hole, forming a third columnar conductor in the fifth contact hole, and forming first and second wiring layers which are electrically connected with the third and second columnar conductors respectively on the third insulator layer in advance of the step of forming the first insulator layer.
In this case, the third and fourth contact holes have depths corresponding to the thickness of the first and second insulator layers and that of the third insulator layer respectively. As compared with the case of forming a contact hole directly exposing a surface of the third impurity region in the first to third insulator layers, therefore, the aspect ratios of the third and fourth contact holes are reduced respectively. Thus, the third and fourth contact holes can be readily formed respectively. Consequently, the third and fourth contact holes are inhibited from defective opening, and the electrical connection between the second wiring layer and the third impurity region is improved. In simultaneous formation of the fourth and fifth contact holes, the part of the surface of the second conductor region exposed on the bottom of the fifth contact hole is thereafter exposed to etching gas for a time corresponding to that up to exposure of the surface of the first columnar conductor on the bottom of the fourth contact hole. As compared with the case of forming a contact hole directly exposing the surface of the third impurity region, therefore, the time for exposing the exposed part to the etching gas is reduced. Thus, the fifth contact hole can be inhibited from partially passing through the second conductor region due to excessive etching of the second conductor region. Consequently, the electrical connection between the first wiring layer and the second conductor region is improved.
According to a seventh preferred aspect of the present invention, the method of fabricating a semiconductor device further includes a step of forming a relay conductor, which is electrically connected with the first columnar conductor, having a larger sectional area than the first columnar conductor on the second insulator layer between the steps of forming the first and second columnar conductors.
In this case, the depth of the fourth contact hole is reduced by a value corresponding to the thickness of the relay conductor. Thus, the aspect ratio of the fourth contact hole is further reduced, so that the fourth contact hole can be further readily opened. Further, the relay conductor has a larger sectional area than the first columnar conductor, whereby its surface can be reliably exposed even if misalignment is caused in photolithography in formation of the fourth contact hole. Thus, the electrical connection between the second wiring layer and the third impurity region is further improved.
According to an eighth preferred aspect of the inventive method of fabricating a semiconductor device, the step of forming the relay conductor is carried out simultaneously with the step of forming the second conductor region.
In this case, the relay conductor can be readily formed simultaneously with formation of the second conductor region, with no requirement for an additional step for forming the relay conductor.
According to a ninth preferred aspect of the present invention, the method of fabricating a semiconductor device further includes steps of forming a plurality of element forming regions and an element isolation region electrically insulating the element forming regions from each other in the first region, forming a first gate electrode portion extending on each element forming region and a second gate electrode, which is connected with the first gate electrode portion, extending on the element isolation region as the gate electrode, and forming a second protective layer to cover the gate electrode in advance of the step of forming the first insulator layer. The method further includes steps of forming an opening exposing a surface of the second protective layer on the first insulator layer located on each element forming region including a portion on the first gate electrode portion and exposing a surface of the element forming region including the first gate electrode portion by removing the exposed part of the second protective layer.
In this case, an opening having a relatively large opening area can be formed in the first insulator layer located in the element forming region. In other words, an opening having a reduced aspect ratio can be formed. Thus, a part of the second protective layer, which is formed to cover the gate electrode at first, covering the first gate electrode portion in the element forming region in particular is excessively etched so that only the second protective layer is exposed on the bottom of the opening without exposing the first gate electrode portion. When the exposed part of the second protective layer is thereafter removed, the surfaces of the first and second impurity regions are exposed substantially with no etching of the first gate electrode portion extending on each element forming region. The remaining part of the second protective layer covering the second gate electrode portion extending on the element isolation region is left unremoved. Thus, the electrical isolation between insulation the first and second conductor regions formed on the element forming region and the gate electrode is improved, and the electrical connection between the source/drain regions of the MOS transistor and the first and second conductor regions is also improved.
According to a tenth preferred aspect of the inventive method of fabricating a semiconductor device, a silicon nitride film is employed as the second protective layer, and a silicon oxide film is employed as the first insulator layer.
In this case, the silicon oxide film can be readily selectively removed while substantially leaving the silicon nitride film.
According to an eleventh preferred aspect of the inventive method of fabricating a semiconductor device, a silicon substrate is employed as the semiconductor substrate, and the step of forming the first conductor layer includes a step of forming a layer of silicon or a silicon-germanium alloy.
In this case, the first conductor layer can be readily formed on a prescribed region of the semiconductor substrate in self alignment. Further, contact resistance between the first conductor layer and the semiconductor substrate can be reduced.
According to a twelfth preferred aspect of the inventive method of fabricating a semiconductor device, a metal selected from a group consisting of titanium, cobalt, zirconium and hafnium is employed as the metal.
In this case, the silicon contained in the first conductor layer and the metal readily cause silicide reaction in formation of the second conductor layer, to readily form metal silicide.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.